The present invention generally relates to a semiconductor integrated circuit device, and more particularly relates to the arrangement of heterojunction bipolar transistors as a high-output power amplifier operating in the microwave region.
In a bipolar transistor, a positive correlation is found between the emitter current and the temperature of the transistor. That is to say, as the temperature of the transistor rises, its emitter current increases. And the increase in emitter current makes the transistor generate heat, thus further raising the temperature of the transistor. As a result, a condition called xe2x80x9cthermal runawayxe2x80x9d might be created and the transistor might possibly be damaged unless appropriate precautions are taken.
Accordingly, a known power amplifier including multiple heterojunction bipolar transistors, in each of which at least two compound semiconductor epitaxial layers with mutually different compositions are stacked, is constructed in the following manner to obtain high output power and good heat dissipation. A power amplifier of this type will be herein called a xe2x80x9cpower HBT devicexe2x80x9d.
Hereinafter, the known power HBT device will be described with reference to FIG. 3.
FIG. 3 illustrates a planar layout for the known power HBT device. As shown in FIG. 3, multiple banks 105 of unit cells 104 are arranged over a semi-insulating GaAs substrate, on which multiple compound semiconductor epitaxial layers are stacked one upon the other. Each unit cell 104 includes unit base, unit collector and unit emitter electrodes 101, 102 and 103. In each unit cell bank 105, two adjacent unit cells 104 are spaced apart from each other by a distance D1, which will be herein called an xe2x80x9cintra-cell-bank cell spacexe2x80x9d. To avoid the thermal runaway by minimizing the thermal interference between the cells and yet not to increase the chip size too much, the intra-cell-bank cell space D1 is defined at an optimum value d.
Two adjacent unit cell banks 105 are placed in parallel to each other and spaced apart from each other by a predetermined distance D2, which will be herein called an xe2x80x9cinter-cell-bank spacexe2x80x9d. And the number of unit cells 104 included in each single unit cell bank 105 and the number of unit cell banks 105 are determined by the required output power and the required chip size.
As shown in FIG. 3, a first unit cell 104 included in a first unit cell bank 105 is spaced apart from a second unit cell 104, which is closest to the first unit cell 104 and included in a second unit cell bank 105 adjacent to the first bank 105, by a distance D3. In other words, if a line is drawn from the center of the first unit cell 104 vertically to the first bank 105 within the substrate plane, then the second unit cell 104 is located at the intersection of the line with the second unit cell bank 105. The distance D3 will be herein called an xe2x80x9cinter-cell-bank cell spacexe2x80x9d and is equal to the inter-cell-bank space D2.
In this manner, multiple unit cells 104, in each of which the unit emitter electrode 103 occupies a relatively small area on the chip, are arranged to be spaced apart from each other by the intra-cell-bank cell space D1 in the direction in which the banks 105 extend (which will be herein called a xe2x80x9cbank directionxe2x80x9d). In the direction vertical to the bank direction, these unit cells 104 are spaced apart from each other by the inter-cell-bank space D2. Thus, compared to an arrangement in which each unit cell 104 is disposed with the periphery of its emitter electrode 103 elongated, the device can dissipate a much greater quantity of heat.
Also, by operating multiple unit cells 104 in parallel, the total periphery length of the emitters increases. As a result, a much greater amount of current can flow and the output power can be increased considerably.
In the known power HBT device, however, the inter-cell-bank cell space D3 should be kept at its optimum value d or more, and therefore, the inter-cell-bank space D2 should also be kept at the optimum value d or more. Thus, in the direction vertical to the bank direction, the width of the chip can be no smaller than a value determined by the optimum value d and the number of unit cell banks 105. In addition, since a great number of unit cells 104 are arranged and equally spaced part from each other on a single chip, heat cannot be dissipated equally from these unit cells 104. That is to say, the heat dissipated from a unit cell 104 located around the center of the chip is different in quantity from the heat dissipated from another unit cell 104 located around an end of the chip.
It is therefore an object of the present invention to provide a semiconductor integrated circuit device that can dissipate a good quantity of heat equally while minimizing the chip area.
To achieve this object, an inventive semiconductor integrated circuit device includes multiple transistor banks over a substrate. The banks are arranged to be substantially parallel to each other in a planar layout of the device. Each said bank includes a plurality of unit transistors, each including a base, an emitter and a collector. In the planar layout of the device, a position of a first one of the transistors is shifted from a position of a second one of the transistors in a direction in which the banks extend. The first and second transistors belong to first and second ones of the banks, respectively. The second bank is adjacent to the first bank. And the second transistor is closer to the first transistor than any other transistor in the second bank.
In the inventive semiconductor integrated circuit device, the position of the first transistor, belonging to the first bank, is shifted from that of the second transistor, belonging to the second bank adjacent to the first bank, in the direction in which the banks extend. Thus, compared to the known arrangement, the distance between most closely disposed transistors is greater in a pair of mutually adjacent banks. Accordingly, the heat generated does not locally concentrate between adjacent transistor banks. As a result, it is possible to dissipate a greater quantity of heat while increasing the number of transistors that can be integrated within the same area.
In one embodiment of the present invention, the device further includes multiple base lines and collector lines over the substrate. Each said bank is associated with one of the base lines and one of the collector lines. Each said base line connects together the bases of the transistors belonging to the associated bank. Each said collector line connects together the collectors of the transistors belonging to the associated bank. And each said bank is interposed between the base and collector lines that are associated with the bank. If the inventive integrated circuit device is implemented as an amplifier using the base and collector as its input and output terminals, respectively, then signal inputting and outputting pads can be connected to the base and collector lines, respectively, without making the base and collector lines intersect each other. As a result, the parasitic capacitance between the signal input and output terminals can be reduced and therefore the gain of the amplifier can be increased.
In another embodiment of the present invention, the transistors in each said bank are preferably substantially equally spaced apart from each other. In such an embodiment, the heat, generated in a bank, does not concentrate locally between adjacent transistors. As a result, a good quantity of heat can be dissipated substantially equally.
In this particular embodiment, the position of the first transistor is preferably shifted from that of the second transistor by half a distance between adjacent ones of the transistors belonging to the first bank in the direction in which the banks extend. In such an embodiment, a pair of transistors, which belong to the first bank and are adjacent to each other in the bank direction, is farthest away from another transistor, which belongs to the second bank and is adjacent to the pair of transistors in the direction vertical to the bank direction. Thus, an even greater quantity of heat can be dissipated in such an arrangement. In addition, the transistors can be arranged more symmetrically over the substrate in both the bank direction and the direction vertical to the bank direction. As a result, the heat can be dissipated even more equally.
More specifically, two adjacent ones of the transistors, which belong to the first bank and include the first transistor, and the second transistor are preferably disposed at respective vertices of an equilateral triangle. In such an embodiment, if any two adjacent transistor banks are equally spaced apart from each other, the distance between unit transistors becomes shortest. That is to say, the transistors can be arranged at the highest density over the substrate, thus greatly reducing the chip area.
In still another embodiment, a distance between two adjacent ones of the banks in a center region of the substrate is greater than a distance between another two adjacent ones of the banks in an end region of the substrate. In general, a greater quantity of heat can be dissipated from around the ends of a substrate than from around the center of the substrate. In this arrangement, however, the heat generated from the transistors is less likely to concentrate at the center of the transistor banks. As a result, an even greater quantity of heat can be dissipated much more equally.
In yet another embodiment, the device preferably further includes a metal film, which covers the substrate and is electrically connected to the emitters of the transistors belonging to the banks. If the inventive semiconductor integrated circuit device is implemented as an amplifier, then the metal film, which covers the substrate and is connected to the emitter electrodes, makes it easier to realize amplification with the emitters grounded. In addition, the metal film can also function as a radiator plate, thus considerably increasing the quantity of heat dissipated.